Method for manufacturing vertical super junction drift layer of power semiconductor devices

ABSTRACT

A method for manufacturing a vertical super junction drift layer of a power semiconductor device. The method includes: a): adopting P+ single crystal silicon to prepare a P+ substrate; b): finishing top processes of the devices on the P+ substrate, forming at least P type region, manufacturing active area and metallizing the top surface of the P+ substrate; c): thinning the back surface of the P+ single crystal silicon; d): selectively implanting H +  ions at the back surface repeatedly and then annealing to form N pillars in the P type region; and e): metallizing the back surface.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation-in-part of International PatentApplication No. PCT/CN2013/090850 with an international filing date ofDec. 30, 2013, designating the United States, now pending, the contentsof which, including any intervening amendments thereto, are incorporatedherein by reference. Inquiries from the public to applicants orassignees concerning this document or the related applications should bedirected to: Matthias Scholl P. C., Attn.: Dr. Matthias Scholl Esq., 245First Street, 18th Floor, and Cambridge, Mass. 02142.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a method for manufacturing a vertical superjunction drift layer of power semiconductor devices.

2. Description of the Related Art

Typically, the super junction (SJ) drift layer of a power semiconductordevice is prepared by (1) multi-epitaxial growth technology, as shown inFIG. 1, or by (2) deep trench etching-epitaxial growth technology, asshown in FIG. 2.

However, the two methods have the following disadvantages: the firstmethod requires strict processing accuracy and thus results in highprocess costs, and second method involves an epitaxial filling process,which is complex and often causes the formation of cavities, which posea reliability risk.

SUMMARY OF THE INVENTION

In view of the above-described problems, it is one objective of theinvention to provide a method for manufacturing a vertical superjunction drift layer of power semiconductor devices.

To achieve the above objective, in accordance with one embodiment of theinvention, there is provided a method for manufacturing a vertical superjunction drift layer of power semiconductor devices, the methodcomprising:

-   -   a) adopting P+ single crystal silicon to prepare P+ substrate;    -   b) finishing top processes of the devices on the P+ substrate,        forming at least P pillar, manufacturing active area and        metallizing the top surface;    -   c) thinning the back surface;    -   d) selectively implanting H⁺ ions at the back surface repeatedly        and then annealing at low temperature to form N pillars in the P        type region; and    -   e) metallizing the back surface.

Specifically, step b also comprises the following steps:

-   -   b1) forming P type region through epitaxial growth on the P+        substrate;    -   b2) forming N type region through epitaxial growth on P type        region;    -   b3) growing a field oxide layer on the N type region;    -   b4) etching active area in the N type region;    -   b5) growing gate oxide on the N type region;    -   b6) depositing and etching polysilicon on the gate oxide;    -   b7) implanting boron ions in N-type region and then performing        drive-in to form P-body base region;    -   b8) implanting arsenic ions in the P-body base region and then        performing drive-in to form N⁺ source region;    -   b9) depositing boro-phospho-silicate-glass (BPSG) on the P-body        base region and then reflowing;    -   b10) etching contact holes on the P-body base region;    -   b11) implanting boron ions in the P-body base region and then        annealing to form P+ contact region; and    -   b12) metallizing the top surface and forming an emitter on the        BPSG.

Further, step d) comprises: selectively implanting H⁺ ions at the backsurface repeatedly and annealing to form the N pillars in the P-typeregion, and repeating implanting H⁺ ions and then annealing to form anN-Field stop layer between the P+ substrate and the super junctionstructure.

Specifically, step b also comprises the following steps:

-   -   b1) forming an N-Field stop layer through epitaxial growth on        the P+ substrate;    -   b2) forming P-type region through epitaxial growth on the        N-Field stop layer;    -   b3) forming N-type region through epitaxial growth on the P-type        region;    -   b4) growing a field oxide layer on N-type region;    -   b5) etching active area in the N type region;    -   b6) growing gate oxide on the N type region;    -   b7) depositing and etching polysilicon on gate oxide;    -   b8) implanting boron ions in N-type region and then performing        drive-in to form P-body base region;    -   b9) implanting arsenic ions in the P-body base region and then        performing drive-in to form N⁺ source region;    -   b10) depositing boro-phospho-silicate-glass (BPSG) on the P-body        base region and then reflowing;    -   b11) etching contact holes on the P-body base region;    -   b12) implanting boron ions in the P-body base region and then        annealing to form P+ contact region; and    -   b13) metallizing the top surface and forming an emitter on the        BPSG.

Specifically, step b also comprises the following steps:

-   -   b1) forming P type region through epitaxial growth on the P+        substrate;    -   b2) implanting phosphorus ions or arsenic ions at the top        surface and then performing drive-in to form N-type region in        the P-type region;    -   b3) growing a field oxide layer on the N type region;    -   b4) etching active area in the N type region;    -   b5) growing gate oxide on the N type region;    -   b6) depositing and etching polysilicon on the gate oxide;    -   b7) implanting boron ions in N-type region and then performing        drive-in to form P-body base region 17;    -   b8) implanting Arsenic ions in the P-body base region and then        performing drive-in to form N⁺ source region;    -   b9) depositing BPSG on the P-body base region and then        reflowing;    -   b10) etching contact holes on the P-body base region;    -   b11) implanting boron ions in the P-body base region and then        annealing to form P+ contact region; and    -   b12) metallizing the top surface and forming an emitter on the        BPSG.

Further, step d) comprises: selectively implanting H⁺ ions at the backsurface repeatedly and annealing to form the N pillars in the P-typeregion, and repeating implanting H⁺ ions and then annealing to form anN-Field stop layer between the P+ substrate and the super junctionstructure.

Specifically, step b comprises the following steps:

-   -   b1) forming an N-Field stop layer through epitaxial growth on        the P+ substrate;    -   b2) forming P-type region through epitaxial growth on the        N-Field stop layer;    -   b3) implanting phosphorus ions or arsenic ions at the top        surface and then performing drive-in to form N-type region in        the P-type region;    -   b4) growing a field oxide layer on the N type region;    -   b5) etching active area in the N type region;    -   b6) growing gate oxide on the N type region;    -   b7) depositing and etching polysilicon on the gate oxide;    -   b8) implanting boron ions in N-type region and then performing        drive-in to form P-body base region;    -   b9) implanting Arsenic ions in the P-body base region and then        performing drive-in to form N⁺ source region;    -   b10) depositing BPSG on the P-body base region and then        reflowing;    -   b11) etching contact holes on the P-body base region;    -   b12) implanting boron ions in the P-body base region and then        annealing to form P+ contact region; and    -   b13) metallizing the top surface and forming an emitter on the        BPSG.

The method of the invention has the advantages of simple manufacturingprocess and reduced process costs.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is described hereinbelow with reference to theaccompanying drawings, in which:

FIG. 1 is a schematic cross-sectional view of SJ-IGBT manufactured byconventional multi-epitaxial growth technology;

FIG. 2 is a schematic cross-sectional view of SJ-IGBT manufactured byconventional deep trench etching-epitaxial growth technology;

FIG. 3 is a flow chart of a method of manufacturing vertical superjunction drift layer, according to the first embodiment of theinvention;

FIG. 4 is a flow chart of a method of manufacturing vertical superjunction drift layer, according to the second embodiment of theinvention;

FIG. 5 is a flow chart of a method of manufacturing vertical superjunction drift layer, according to the third embodiment of theinvention;

FIG. 6 is a flow chart of a method of manufacturing vertical superjunction drift layer, according to the fourth embodiment of theinvention;

FIG. 7 is a schematic cross-sectional view of SJ-IGBT in accordance withan embodiment;

FIG. 8 is a schematic cross-sectional view of P+ single crystalsubstrate according to an embodiment that provides growing asemiconductor layer by epitaxy;

FIG. 9 is a schematic cross-sectional view of growing P-type regionthrough epitaxial growth in accordance with an embodiment;

FIG. 10 is a schematic cross-sectional view of growing N-type regionthrough epitaxial growth according to an embodiment;

FIG. 11 is a schematic cross-sectional view of growing field oxide inaccordance with an embodiment;

FIG. 12 is a schematic cross-sectional view of etching active areaaccording to an embodiment;

FIG. 13 is a schematic cross-sectional view of growing gate oxide inaccordance with an embodiment;

FIG. 14 is a schematic cross-sectional view of depositing and etching ofN⁺ polysilicon according to an embodiment;

FIG. 15 is a schematic cross-sectional view of boron ions implanting anddrive-in of P-body base region in accordance with an embodiment;

FIG. 16 is a schematic cross-sectional view of arsenic implanting anddrive-in of N⁺ source region according to an embodiment;

FIG. 17 is a schematic cross-sectional view of deposition and reflow ofBPSG and view of contact holes etching in accordance with an embodiment;

FIG. 18 is a schematic cross-sectional view of boron implanting anddrive-in of P+ contact region according to an embodiment;

FIG. 19 is a schematic cross-sectional view of metallizing the topsurface and thinning at the back surface in accordance with anembodiment;

FIG. 20 is a schematic cross-sectional view of selectively H⁺ ions atthe back surface repeatedly according to an embodiment;

FIG. 21 is a schematic cross-sectional view of H⁺ ions at the backsurface repeatedly in accordance with an embodiment;

FIG. 22 is a schematic cross-sectional view of annealing at lowtemperature according to an embodiment; and

FIG. 23 is a schematic cross-sectional view of metallizing the backsurface in accordance with an embodiment.

DETAILED DESCRIPTION OF THE EMBODIMENTS

For further illustrating the invention, experiments detailing a methodfor manufacturing a vertical super junction drift layer of powersemiconductor devices are described below. It should be noted that thefollowing examples are intended to describe and not to limit theinvention.

As shown in FIG. 3, the first embodiment of the invention provides amethod for manufacturing a vertical super junction drift layer of powersemiconductor devices, the method comprising the following steps:

-   -   1) adopting P+ single crystal silicon to prepare P+ substrate        11;    -   2) forming P type region 12 through epitaxial growth on the P+        substrate 11;    -   3) forming N type region 13 through epitaxial growth on P type        region 13;    -   4) growing a field oxide layer 14 on the N type region 13;    -   5) etching active area in the N type region 13;    -   6) growing gate oxide 15 on the N type region 13;    -   7) depositing and etching polysilicon 16 on gate oxide 15;    -   8) implanting Boron ions in N-type region 13 and then performing        drive-in to form P-body base region 17;    -   9) implanting arsenic ions in the P-body base region 17 and then        performing drive-in to form N⁺ source region;    -   10) deposition BPSG 19 on the P-body base region 17 and then        reflowing;    -   11) etching contact holes 20 on the P-body base region 17;    -   12) implanting Boron ions in the P-body base region 17 and then        annealing to form P+ contact region 21;    -   13) metallizing the top surface and forming emitter 22 on BPSG        19.    -   14) thinning the back surface;    -   15) selectively implanting H⁺ ions at the back surface        repeatedly and then annealing at low temperature to form N        pillars 25 in the P type region 12;    -   16) metallizing the back surface.

As shown in FIG. 4, the second embodiment of the invention provides amethod for manufacturing a vertical super junction drift layer of powersemiconductor devices. Based on the first manufacturing method, thesecond one provides a simplified process to form an N-Field stop layer24. The detailed process is as follows. after selectively implanting H⁺ions at the back surface repeatedly and annealing at low temperature toform N pillars 25 in the P-type region 12, implant H⁺ ions repeatedlyonce again and then anneal to form the N-Field stop layer 24 between P+substrate 11 and super junction structure.

As shown in FIG. 5, the third embodiment of the invention provides amethod for manufacturing a vertical super junction drift layer of powersemiconductor devices, comprising the following steps:

-   -   1) adopting P+ single crystal silicon to prepare P+ substrate        11;    -   2) forming P type region 12 through epitaxial growth on the P+        substrate 11;    -   3) implanting phosphorus ions or arsenic ions at the top surface        and then performing drive-in to form N-type region 13 in the        P-type region 12;    -   4) growing a field oxide layer 14 on the N type region 13;    -   5) etching active area in the N type region 13;    -   6) growing gate oxide 15 on the N type region 13;    -   7) depositing and etching polysilicon 16 on gate oxide 15;    -   8) implanting boron ions in N-type region 13 and then performing        drive-in to form P-body base region 17;    -   9) implanting Arsenic ions in the P-body base region 17 and then        performing drive-in to form N⁺ source region;    -   10) deposition of BPSG 19 on the P-body base region 17 and then        reflowing;    -   11) etching contact holes 20 on the P-body base region 17;    -   12) implanting boron ions in the P-body base region 17 and then        annealing to form P+ contact region 21;    -   13) metallizing the top surface and forming emitter 22 on BPSG        19;    -   14) thinning the back surface;    -   15) selectively implanting H⁺ ions at the back surface        repeatedly and then annealing at low temperature to form N        pillars 25 in the P type region 12; and    -   16) metallizing the back surface.

As shown in FIG. 6, the fourth embodiment of the invention provides amethod for manufacturing a vertical super junction drift layer of powersemiconductor devices. Based on the third manufacturing method, thefourth one provides a simplified process to form an N-Field stop layer24. The detailed process is as follows. after selectively implanting H⁺ions at the back surface repeatedly and annealing at low temperature toform N pillars 25 in the P-type region 12, implant H⁺ ions repeatedlyonce again and then anneal to form the N-Field stop layer 24 between P+substrate 11 and super junction structure.

According to the above technical solutions, the difference between thefirst manufacturing method and the third one is the forming method ofN-type region 13. For the first and third technical solutions, theN-type region 13 is formed by epitaxial growth and drive-in,respectively.

The essence of the invention is that P+ single crystal is chosen assubstrate. Firstly, P-type layer is grown on the surface of P+ singlecrystal substrate through epitaxial growth, which acts asvoltage-sustaining layer of the super junction structure. Then N-typelayer is formed on the surface of P-type layer through epitaxy or ionsimplanting and drive-in, wherein MOS structure is formed. After thecompletion of top process, the back surface of the device is thinned.Then the N pillars in the super junction structure is formed through H⁺ions selectively implantation repeatedly and annealing at lowtemperature. after selectively implanting H⁺ ions at the back surfacerepeatedly and annealing at low temperature, H⁺ ions can be implantedrepeatedly at the back surface once again and annealing is done at thesame temperature if an N-Field stop layer between the super junctionstructure and P+ substrate is needed for the device. Then, a superjunction structure with the N-Field stop layer can be obtained.

The working principle of this invention is as follows:

The basic technical solution of the invention is that the P-type layerand the N-type layer are grown on the P+ single crystal substratethrough epitaxial growth. The P-type layer is used to sustain voltageand the N-type layer is used to form a planar gate MOS structure at thetop surface. After the completion of the top planar gate MOS process andthinning, H⁺ ions selective implantation and H⁺ ions implantation aredone in order. Then annealing at low temperature to activate the donorsrelated to H⁺ ions so as to form N-type pillars and an N-Field stoplayer 24, decrease the concentration of recombination centers andbroaden the distribution range of peak concentrations. Then theprocesses of metallizing the back surface and so on are done to form thecomplete structure.

Because the radius and mass of hydrogen are both the smallest amongchemical elements, the diffusion velocity of H⁺ ion in silicon is fast.Especially in the up to 1000 degree centigrade thermal process, all ofthe H⁺ ions maybe diffuse to the surface, which results in nonuniformconcentration distribution. Meanwhile, H⁺ ions are easy to beaccelerated to own high energy and high penetration, which is easy tocause deep implantation. For example, when H⁺ ions are implanted withthe energy of 2 MeV, the projected range Rp is 47.69 μm and thecorresponding vertical discrete deviation and lateral discrete deviationare 2.04 μm and 2.56 μm, respectively. When H⁺ ions are implanted withthe energy of 3 MeV, the projected range Rp can reach up to 92.05 μm andthe corresponding vertical discrete deviation and lateral discretedeviation are 4.06 μm and 4.66 μm, respectively. When H⁺ ions areimplanted with high energy, a large number of defects and recombinationcenters are produced within the scope of the projected range. Throughlow temperature annealing, the donors related to hydrogen (for example:thermal donors at shallow energy level and so on) can be activated andthen the P-type epitaxial layer is changed to N pillars with a neededpeak concentration. Moreover, the concentration of recombination centers(for example: divacancies, oxygen-vacancy compounds) is reduced. Thehigh energy implantation of H⁺ ions will introduce an N-type peakconcentration near projected range Rp. From the top surface of siliconto the location of Rp, the N-type concentration is prone to constantvalue. Through H⁺ implantation repeatedly, implantation energy and doseoptimization, the concentration uniformity within the scope of theprojected range can be guaranteed. In the process of low temperatureannealing, the temperature is usually controlled in the range of 350-420degree centigrade. If the annealing temperature is raised to the rangeof 420-550 degree centigrade, the zone with N-type peak concentrationcaused by H⁺ ions will be broadened significantly and the number of H⁺ions implantation can be decreased. Table 1 shows the correspondingprojected range Rp, vertical discrete deviation and lateral discretedeviation when the energy of H⁺ ions implantation is in the range of0.5-3.5 MeV.

TABLE 1 Test-data Table With Corresponding Projected Range Rp, VerticalDiscrete Deviation and Lateral Discrete Deviation When the Energy of H⁺ions Implantation is in the Range of 0.5-3.5 MeV Implantation energyProjected range Vertical discrete Lateral discrete E/MeV R_(P)/μmdeviation/μm deviation/μm 0.5 5.99 0.31 0.44 0.55 6.85 0.35 0.49 0.67.75 0.39 0.54 0.65 8.69 0.42 0.59 0.7 9.67 0.46 0.64 0.8 11.74 0.570.75 0.9 13.97 0.68 0.87 1.00 16.33 0.79 1.00 1.10 18.84 0.90 1.13 1.2021.48 1.00 1.26 1.30 24.28 1.11 1.40 1.40 27.22 1.21 1.55 1.50 30.291.32 1.71 1.60 33.50 1.44 1.87 1.70 36.85 1.55 2.03 1.80 40.33 1.66 2.202.00 47.69 2.04 2.56 2.25 57.61 2.56 3.03 2.50 68.32 3.07 3.54 2.7579.80 3.56 4.08 3.00 92.05 4.06 4.66 3.25 105.03 4.56 5.26 3.50 118.765.07 5.89

As shown in Table 1, for different blocking voltage levels, the numberand energy of H⁺ implantation can be determined according to the neededprojected range. The ratio of vertical discrete deviation, lateraldiscrete deviation to projected range for H⁺ ions implantation is only5%. The foundation for super junction structure achieving high blockingvoltage is the charge balance between P pillar and N pillars. The higherfor the ratio of charge unbalance, the more the blocking voltage willdecrease. As the ratio of vertical discrete deviation, lateral discretedeviation to projected range for H⁺ ions implantation is far smallerthan the corresponding values for other ions, the process difficulty forcharge balance is reduced.

EXAMPLE 1

Example 1 adopts the technical solution of the invention to manufacturea 600 V SJ-IGBT (the structure is as shown in FIG. 7). The detailedprocess is as follows:

(1) Prepare the material of P+ single crystal substrate 11, as shown inFIG. 8. The thickness and resistivity of P+ single crystal substrate 11are 400-600 μm and 0.0135-0.0375 Ω·cm. The impurity is boron.

(2) Forming P type region 12 through epitaxial growth, as shown in FIG.9. The thickness and resistivity of P-type region 12 are 50 μm and 13.2Ω·cm, respectively. The temperature for epitaxial growth is 1000-1200degree centigrade and the impurity is boron.

(3) Forming N type region 13 through epitaxial growth, as shown in FIG.10. The thickness and resistivity of P-type region 13 are 3 μm and 4.5∩·cm, respectively. The temperature for epitaxial growth is 1000-1200degree centigrade and the impurity is phosphorus or arsenic.

(4) Growing a field oxide layer 14, as shown in FIG. 11. The temperaturefor growing field oxide 14 is 1000-1200 degree centigrade and thethickness of field oxide is 0.5-1.5 μm.

(5) Etching active area, as shown in FIG. 12.

(6) Growing gate oxide layer 15, as shown in FIG. 13. The temperaturefor growing field oxide 15 is 1000-1100 degree centigrade and thethickness of field oxide is 40-120 nm

(7) Depositing and etching polysilicon 16, as shown in FIG. 14. Theimpurity is phosphorus or arsenic and the concentration is 5e19-1e20cm⁻³. The deposition temperature is 850 degree centigrade and thethickness of polysilicon is 0.8 μm.

(8) The boron implantation and drive-in of P-body base area, as shown inFIG. 15. The implantation dose and energy of boron ions are 2e13 cm⁻²and 80 KeV, respectively. The drive-in temperature and time are 1100degree centigrade and 90 minutes, respectively.

(9) The arsenic implantation and drive-in of N⁺ source area, as shown inFIG. 16. The implantation dose and energy of arsenic ions are 2e15 cm⁻²and 80 KeV, respectively. The drive-in temperature and time are 950degree centigrade and 40 minutes, respectively.

(10) Deposition and reflowing of BPSG 19 and etching contact holes 20,as shown in FIG. 17. The temperature for deposition is 850 degreecentigrade and the thickness of BPSG is 1 μm, respectively. The reflowtemperature and time are 975 degree centigrade and 50 minutes,respectively.

(11) The boron implantation and annealing of P+ contact area, as shownin FIG. 18. The implantation dose and energy of boron ions are 5e15 cm⁻²and 60 KeV, respectively. The annealing temperature and time are 850degree centigrade and 40 minutes, respectively.

(12) Metallizing the top surface and depositing aluminum layer withthickness of 1-4 μm to form emitter 22, as shown in FIG. 19. Meanwhile,thin the back surface of the silicon to 53 μm.

(13) Selectively implanting H⁺ ions at the back surface repeatedly, asshown in FIG. 20. The implantation energy, projected range and doseevery time are as follows in order:

The 1^(st) time: 1 MeV, R_(P)=16.33 μm, 8e13-3e14 cm⁻²;

The 2^(nd) time: 1.2 MeV, R_(P)=21.48 μm, 1e14-5e14 cm⁻²;

The 3^(rd) time: 1.4 MeV, R_(P)=27.22 μm, 2e14-6e14 cm⁻²;

The 4^(th) time: 1.6 MeV, R_(P)=33.50 μm, 3e14-8e14 cm⁻²;

The 5^(th) time: 1.8 MeV, R_(P)=40.33 μm, 5e14-9e14 cm⁻²;

The 6^(th) time: 2 MeV, R_(P)=47.69 μm, 7e14-1e15 cm⁻².

(14) Implanting H⁺ ions at the back surface repeatedly, as shown in FIG.21. The implantation energy, projected range and dose every time are asfollows in order:

The 1^(st) time: 700 KeV, R_(P)=9.67 μm, 8e14-3e15 cm⁻²;

The 2^(nd) time: 800 KeV, R_(P)=11.74 μm, 1e15-5e15 cm⁻².

(15) Annealing at low temperature to form N pillars 25 and an N-Fieldstop layer 24. The annealing temperature and time are 350-470 degreecentigrade and 180-300 minutes.

(16) Metallizing the back surface to form emitter 26, as shown in FIG.23. The thickness of aluminum deposited is 1-4 μm.

Unless otherwise indicated, the numerical ranges involved in theinvention include the end values. While particular embodiments of theinvention have been shown and described, it will be obvious to thoseskilled in the art that changes and modifications may be made withoutdeparting from the invention in its broader aspects, and therefore, theaim in the appended claims is to cover all such changes andmodifications as fall within the true spirit and scope of the invention.

The invention claimed is:
 1. A method for manufacturing a vertical superjunction drift layer of power semiconductor devices, the methodcomprising: a): adopting P+ single crystal silicon to prepare a P+substrate; b): finishing top processes of the devices on the P+substrate, forming at least P type region, manufacturing active area andmetallizing a top surface of the P+ substrate; c): thinning a backsurface of the P+ single crystal silicon; d): selectively implanting H⁺ions at the back surface repeatedly and then annealing to form N pillarsin the P type region; and e): metallizing the back surface.
 2. Themethod of claim 1, wherein b) comprises the following steps: b1: formingP type region through epitaxial growth on the P+ substrate; b2: formingN type region through epitaxial growth on the P type region; b3: growinga field oxide layer on the N type region; b4: etching active area in theN type region; b5: growing gate oxide on the N type region; b6:depositing and etching polysilicon on the gate oxide; b7: implantingboron ions in the N-type region and then performing drive-in to formP-body base region; b8: implanting arsenic ions in the P-body baseregion and then performing drive-in to form N⁺ source region; b9:depositing boro-phospho-silicate-glass (BPSG) on the P-body base regionand then reflowing; b10: etching contact holes on the P-body baseregion; b11: implanting boron ions in the P-body base region and thenannealing to form P+ contact region; and b12: metallizing the topsurface and forming an emitter on the BPSG.
 3. The method of claim 2,wherein d) comprises: selectively implanting H⁺ ions at the back surfacerepeatedly and annealing to form the N pillars in the P-type region, andrepeating implanting H⁺ ions and then annealing to form an N-Field stoplayer between the P+ substrate and the super junction structure.
 4. Themethod of claim 1, wherein b) comprises the following steps: b1: formingan N-Field stop layer through epitaxial growth on the P+ substrate; b2:forming P-type region through epitaxial growth on the N-Field stoplayer; b3: forming N-type region through epitaxial growth on the P-typeregion; b4: growing a field oxide layer on N-type region; b5: etchingactive area in the N type region; b6: growing gate oxide on the N typeregion; b7: depositing and etching polysilicon on the gate oxide; b8:implanting boron ions in N-type region and then performing drive-in toform P-body base region; b9: implanting arsenic ions in the P-body baseregion and then performing drive-in to form N⁺ source region; b10:depositing BPSG on the P-body base region and then reflowing; b11:etching contact holes on the P-body base region; b12: implanting boronions in the P-body base region and then annealing to form P+ contactregion; and b13: metallizing the top surface and forming an emitter onthe BPSG.
 5. The method of claim 1, wherein b) comprises the followingsteps: b1: forming P type region through epitaxial growth on the P+substrate; b2: implanting phosphorus ions or arsenic ions at the topsurface and then performing drive-in to form N-type region in the P-typeregion; b3: growing a field oxide layer on the N type region; b4:etching active area in the N type region; b5: growing gate oxide on theN type region; b6: depositing and etching polysilicon on the gate oxide;b7: implanting boron ions in N-type region and then performing drive-into form P-body base region; b8: implanting Arsenic ions in the P-bodybase region and then performing drive-in to form N⁺ source region; b9:depositing BPSG on the P-body base region and then reflowing; b10:etching contact holes on the P-body base region; b11: implanting boronions in the P-body base region and then annealing to form P+ contactregion; and b12: metallizing the top surface and forming an emitter onthe BPSG.
 6. The method of claim 5, wherein d) comprises: selectivelyimplanting H⁺ ions at the back surface repeatedly and annealing to formthe N pillars in the P-type region, and repeating implanting H⁺ ions andthen annealing to form an N-Field stop layer between the P+ substrateand the super junction structure.
 7. The method of claim 1, wherein b)comprises the following steps: b1: forming an N-Field stop layer throughepitaxial growth on the P+ substrate; b2: forming P-type region throughepitaxial growth on the N-Field stop layer; b3: implanting phosphorusions or arsenic ions at the top surface and then performing drive-in toform N-type region in the P-type region; b4: growing a field oxide layeron the N type region; b5: etching active area in the N type region; b6:growing gate oxide on the N type region; b7: depositing and etchingpolysilicon on the gate oxide; b8: implanting boron ions in N-typeregion and then performing drive-in to form P-body base region; b9:implanting Arsenic ions in the P-body base region and then performingdrive-in to form N⁺ source region; b10: depositing BPSG on the P-bodybase region and then reflowing; b11: etching contact holes on the P-bodybase region; b12: implanting boron ions in the P-body base region andthen annealing to form P+ contact region; and b13: metallizing the topsurface and forming an emitter on the BPSG.